TMC6200 DATASHEET (Rev. 1.01 / 2018-NOV-15)
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8 External Reset
The chip is loaded with default values during power on via its internal power-on reset. In order to
reset the chip to power on defaults, any of the supply voltages monitored by internal reset circuitry
(VSA, +5VOUT or VCC_IO) must be cycled. As +5VOUT is the output of the internal voltage regulator, it
cannot be cycled via an external source except by cycling VSA. It is easiest and safest to cycle VCC_IO
in order to completely reset the chip. Also, current consumed from VCC_IO is low and therefore it has
simple driving requirements. Due to the input protection diodes not allowing the digital inputs to rise
above VCC_IO level, all inputs must be driven low during this reset operation. When this is not
possible, an input protection resistor may be used to limit current flowing into the related inputs.
9 Clock Oscillator and Input
The clock is the timing reference for the internal BBM time generator and is used to operate the SPI
interface. The factory-trimmed on-chip clock oscillator provides timing which is sufficient for most use
cases.
9.1 Using the Internal Clock
Directly tie the CLK input to GND near to the IC if the internal clock oscillator is to be used. It
provides a precision of roughly +-4%, which is precise enough for BBM operation.
9.2 Using an External Clock
When an external clock is available, a frequency of 4 MHz to 30 MHz is possible. Especially with low
clock frequency, make sure, that the SPI timing is kept in order to ensure proper SPI operation. The
duty cycle of the clock signal is uncritical, as long as minimum high or low input time for the pin is
satisfied (refer to electrical characteristics). Make sure, that the clock source supplies clean CMOS
output logic levels and steep slopes when using a high clock frequency. The external clock input is
enabled with the second positive polarity seen on the CLK input.
Attention
Switching off the external clock frequency prevents the driver from operating normally. Therefore, an
internal watchdog switches back to internal clock in case the external signal is missing for more than
roughly 32 internal clock cycles.
9.2.1 Considerations on the Frequency
A higher frequency allows more precise BBM timing and faster SPI operation. A lower frequency will
reduce power consumption of the IC, which especially at high VSA supply voltages reduces overall
power consumption by a few 100mW. However, the internal timing should be sufficient for most
applications.
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