TMC4361 DATASHEET (Rev. 2.68 / 2015-Apr-14) Preliminary
15
START INPUT PIN
Every fourth clock cycle is sampled and the sampled input bit is valid.
CLK
START
internal Step
input signal
START
internal Dir
input signal
Figure 6.3 START input pin: SR_S = 2, FILT_L_S = 0
ENCODER INTERFACE INPUT PINS
Every clock cycle bit is sampled. Eight sampled input bits must be equal to be a valid input voltage.
CLK
B_SDI
internal B
input signal
N
internal N
signal
Figure 6.4 Encoder interface input pins: SR_ENC_IN = 0, FILT_L_ENC_IN = 7
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