TE
tmCH
T436416A
Page Write cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
C S
H IG H
R A S
C A S
A D D R
B A
*N o te2
R A a
C A a R B b
C B b
C A c
C B d
R A a
R B b
A 1 0 /A P
D A a0
D A a1
D A a2
D A a3
D B b 0
D B b 1
D B b 2
D B b 3
D A c0
D A c1
D B d 0
D B d 1
D Q
tC D L
tR D L
W E
*N o te1
D Q M
R o w A ctiv e
(A -B an k )
R o w A ctiv e
(B -B an k )
W rite (B -
B an k )
W rite (A -
B an k )
W rite (B -
B an k )
P rech arg e
(A -B an k )
W rite (A -
B an k )
:D on't care
*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.19
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
