TE
tmCH
T436416A
Read & Write Cycle at Same Bank @Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C L O C K
H IG H
C K E
* N o te 1
tR
C
C S
tR
C D
R A S
* N o te 2
C A S
A D D R
R a
C a 0
R b
C b 0
B A
A 1 0 /A P
R a
R b
tO
H
C L = 2
D Q
Q a 0 Q a 1 Q a 2 Q a 3
D b 0 D b 1 D b 2 D b 3
tR
A
C
* N o te 3
tR D L
* N o te 4
tS A
C
tO
H
tS H Z
C L = 3
Q a 0 Q a 1 Q a 2 Q a 3
D b 0 D b 1 D b 2 D b 3
tR
D L
* N o te 3
* N o te 4
tS A
C
tS H
Z
W E
D Q M
R o w
R e a d ( A -
B a n k )
P r e c h a r g
( A -
B a n k )
R o w A c tiv e
( A - B n a k )
W
rite ( A -
B n a k )
P r e c h a r g e
( a - B n a k )
A c tiv e ( A -
B a n k )
e
:D o n 't c a re
*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is
available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3. Access time from Row active command. tCC*(tRCD+CAS latency-1)+tSAC
4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.16
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
