TE
tmCH
T436416A
Read & Write Cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C L O C K
H I G H
C K E
C S
R A S
C A S
A D D R
R a
R b
C a
C b
B A
A 1 0 /A P
R a
R b
C L = 2
D Q
Q a 0 Q a 1 Q a 2 Q a 3
D b 0
D b 2 D b 3
D b 1
C L = 3
Q a 0 Q a 1 Q a 2 Q a 3
D b 0 D b 1 D b 2 D b 3
W E
D Q M
R o w A c tiv e
( A - B a n k )
R o w A c tiv e
( B - B a n k )
C L = 2 A u to
W
rite w ith A u to
A u to P re c h a rg e
S ta r t P o in t ( A -
B a n k )
P r e c h a r g e S ta r t
P o in t ( A - B a n k )
P r e c h a r g e ( B -
B a n k )
R e a d w ith A u to
p r e c h a r g e (A -
B a n k )
C L = 3 A u to
:D o n 't c a r e
P r e c h a r g e S ta r t
P o in t ( A - B a n k )
*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.21
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
