TE
tmCH
T436416A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C L O C K
H I G H
C K E
C S
tR C D
R A S
* N o te 2
tC C D
C A S
A D D R
R a
C a 0
C c 0
C d 0
C b 0
B A
A 1 0 /A P
tR
D
L
Q b 1
Q b 2
Q b 0
D d 1
C L = 2
D Q
Q a 0 Q a 1
D c 0 D c 1 D d 0
tC
D
L
Q b 0
C L = 3
Q a 0 Q a 1
Q b 1
D c 0 D c 1 D d 0 D d 2
W E
* N o te 3
* N o te 1
D Q M
R o w A c tiv e
( A - B n a k )
R e a d ( A -
B n a k )
R e a d ( A -
B n a k )
W
rite ( A -
B n a k )
W
rite ( A -
B n a k )
P r e c h a r g e
( A - B n a k )
:D o n 't c a r e
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to
avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before
end of burst. Input data after Row precharge cycle will be masked internally.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.17
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
