TE
tmCH
T436416A
SIMPLIFIED TRUTH TABLE
BA
0,1
A9~A0,
A11
COMMAND
Mode Register Set
Auto Refresh
CKEn-1 CKEn
DQM
X
A10/AP
Note
CS
L
RAS CAS WE
Register
Refresh
H
X
H
L
L
L
X
1,2
H
L
L
L
H
X
X
3
Entry
Exit
L
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
L
H
X
X
X
X
3
Bank Active & Row Address
H
V
V
V
Row Address
Column
Address
(A0~A7)
Column
Address
(A0~A7)
Auto Precharge Disable
Auto Precharge Enable
Read Column
Address
L
H
L
H
H
X
L
H
L
H
X
4,5
Auto Precharge Disable
Auto Precharge Enable
Write & Column
Address
H
H
X
X
L
L
H
H
L
L
L
X
X
4,5
6
Burst Stop
H
X
Bank Selection
Both Banks
V
X
L
H
Precharge
H
X
L
L
H
L
X
4
Entry
H
L
X
X
V
X
X
V
X
X
V
X
H
L
L
X
X
Clock Suspend or
Active Power Down
X
X
Exit
H
Entry
H
L
H
L
X
H
X
V
X
H
X
V
X
H
X
V
H
L
X
Precharge Power Down
Mode
Exit
L
H
X
V
DQM
H
X
7
X
X
H
H
H
L
X
H
X
H
X
H
No Operation Command
X
X
(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
Notes :
1. OP Code : Operation Code. A0~A11 , BA0~BA1 : Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.
4. BA0~BA1 : Bank select address.
If both BA0 and BA1 are ’Low’ : at read , write , row active and precharge , bank A is selected.
If both BA0 is ‘Low’ and BA1 is ‘High’ : at read , write , row active and precharge , bank B is selected.
If both BA0 is ‘High’ and BA1 is ‘Low’ : at read , write , row active and precharge , bank C is selected.
If both BA0 and BA1 are ’High’ : at read , write , row active and precharge , bank D is selected
If A10/AP is ‘High’ : at row precharge , BA0 and BA1 ignored and all banks are selected.
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TM Technology Inc. reserves the right
to change products or specifications without notice.
P.12
Publication Date: MAY. 2003
Revision: B
TMT [ TAIWAN MEMORY TECHNOLOGY ]
