UCC28070-Q1
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SLUSA71A –JULY 2010–REVISED JUNE 2011
The output capacitor maximum low-frequency zero-to-peak ripple voltage is closely approximated by:
Pinavg ´ XCout
Pinavg
v
=
=
0 pk
Voutavg
Voutavg ´2p ´ f2LF ´Cout
(27)
where PIN(avg) is the total maximum input power of the interleaved-PFC pre-regulator, VOUT(avg) is the average
output voltage and COUT is the output capacitance.
VSENSEpk = vopkxkR, where kR is the gain of the resistor-divider network on VSENSE.
Thus, for k3rd% of allowable 3rd-harmonic distortion on the input current attributable to the VAO ripple,
k
3rd ´64mV ´Voutavg ´2p f2LF ´Cout
gmv ´kR ´ Pinavg
ZOV ( f
=
)
2 LF
(28)
(29)
This impedance on VAO is set by a capacitor (Cpv), where CPV = 1/( 2πf2LFxZOV(f2LF)) therefore,
gmv ´kR ´ Pinavg
Cpv =
k
3rd ´64mV ´Voutavg ´( 2p f )2 ´Cout
2LF
The voltage-loop unity-gain cross-over frequency (fVXO) may now be solved by setting the open-loop gain equal
to 1:
æ
ö
Pinavg ´ XCout
Tv( fVXO ) = GBST ´GVEA ´k =
´ g ´ X
(
mv
´k =1
Cpv R
ç
÷
)
R
ç
÷
DVVAO ´Voutavg
è
ø
(30)
gmv ´kR ´ Pinavg
DVVAO ´Voutavg ´ 2p 2 ´Cpv´Cout
2
fVXO
=
( )
so,
(31)
The "zero-resistor" (RZV) from the zero-placement network of the compensation may now be calculated. Together
with CPV, RZV sets a pole right at fVXO to obtain 45° phase margin at the cross-over.
1
Rzv =
2p fVXO ´Cpv
Thus,
(32)
Finally, a zero is placed at or below fVXO/6 with capacitor CZV to provide high gain at dc but with a breakpoint far
enough below fVXO so as not to significantly reduce the phase margin. Choosing fVXO/10 allows one to
approximate the parallel combination value of CZV and CPV as CZV, and solve for CZV simply as:
10
Czv =
»10´Cpv
2p fVXO ´ Rzv
(33)
By using a spreadsheet or math program, CZV, RZV, and CPV may be manipulated to observe their effects on fVXO
and phase margin and %-contribution to 3rd-harmonic distortion (see note below). Also, phase margin may be
checked as PIN(avg) level and system parameter tolerances vary.
NOTE
The percent of 3rd-harmonic distortion calculated in this section represents the
contribution from the f2LF voltage ripple on COUT only. Other sources of distortion, such as
the current-sense transformer, the current synthesizer stage, even distorted VIN, etc., can
contribute additional 3rd and higher harmonic distortion.
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31
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