TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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Table 3-2. VBUS Registers Summary
VBUS
SUBADDRESS
REGISTER NAME
DEFAULT
R/W(1)
(2)(3)
Reserved
00 0000h – 80 051Bh
80 051Ch – 80 051Fh
80 0520h – 80 0526h
80 0527h – 80 052Bh
80 052Ch – 80 0534h
80 0535h – 80 053Fh
80 0540h – 80 0543h
80 0544h – 80 05FFh
80 0600h – 80 0611h
80 0612h – 80 06FFh
80 0700h – 80 070Ch
80 070Dh – A0 005Dh
A0 005Eh
VDP Closed Caption Data
VDP WSS/CGMS data
R
R
(2)(3)
Reserved
VDP VITC Data
R
R
(2)(3)
Reserved
VDP V-Chip Data
(2)(3)
Reserved
VDP General Line Mode and Address
FFh, 00h
R/W
R
(2)(3)
Reserved
VDP VPS/Gemstar EPG Data
(2)(3)
Reserved
Analog Output Control 2
B2h
00h
R/W
R/W
(2)(3)
Reserved
A0 005Fh – B0 005Fh
B0 0060h
Interrupt Configuration Register
(2)(3)
Reserved
B0 0062h – B0 0064h
B0 0065h
Interrupt Mask 1
Interrupt Raw Status 1
Interrupt Status 1
Interrupt Clear 1
Reserved(2)(3)
R
R
R
R
B0 0069h
B0 006Dh
B0 0071h
B0 0073h – FF FFFFh
(1) R = Read only, W = Write only, R/W = Read and write
(2) Register addresses not shown in the register map summary are reserved and must not be written to.
(3) Writing to or reading from any value labeled "Reserved" register may cause erroneous operation of the TVP5160 decoder. For registers
with reserved bits, a 0b must be written to reserved bit locations unless otherwise stated.
42
Internal Control Registers
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