TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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Table 3-10. Luminance Processing Control 1
Subaddress 06h
Default 00h
7
6
5
4
3
2
1
0
Reserved
Pedestal
Reserved
VBI raw
Reserved
Luminance signal delay [2:0]
Pedestal:
0 = 7.5 IRE pedestal is present on the analog video input signal (default)
1 = Pedestal is not present on the analog video input signal
VBI raw:
0 = Disable (default)
1 = Enable
During the duration of the vertical blanking as defined by VBLK start and stop registers 22h through 25h, the chroma samples are replaced
by luma samples. This feature may be used to support VBI processing performed by an external device during the vertical blanking interval.
To use this bit, the output format must be the 10-bit, ITU-R BT.656 mode.
Luminance signal delay [2:0]: Luminance signal delays respect to chroma signal in 1× pixel clock increments.
011 = 3 pixel clocks delay
010 = 2 pixel clocks delay
001 = 1 pixel clock delay
000 = 0 pixel clock delay (default)
111 = –1 pixel clock delay
110 = –2 pixel clocks delay
101 = –3 pixel clocks delay
100 = 0 pixel clock delay
Table 3-11. Luminance Processing Control 2
Subaddress 07h
Default
00h
7
6
5
4
3
2
1
0
Luma filter select [1:0]
Reserved
Peaking gain [1:0]
Reserved
Luma filter selected [1:0]:
00 = Luminance adaptive comb enable (default on CVBS and SECAM)
01 = Luminance adaptive comb disable (trap filter selected)
10 = Luma comb/trap filter bypassed (default on S-Video, component mode)
11 = Reserved
Peaking gain [1:0]:
00 = 0 (default)
01 = 0.5
10 = 1
11 = 2
46
Internal Control Registers
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