TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
2.9.2 I2C Operation
Data transfers occur utilizing the following formats.
Read from I2C control registers
receive
data
S
10111000
ACK
subaddress
ACK
S
10111001
ACK
NAK
P
Write to I2C control registers
S
10111000
ACK
subaddress
ACK
send data
ACK
P
S = I2C bus start condition
P = I2C bus stop condition
ACK = Acknowledge generated by the slave
NAK = Acknowledge generated by the master, for multiple byte read master will ACK each
byte except the last byte
Subaddress = Subaddress byte
Data = Data byte
I2C bus address = In the example shown, I2CA0/I2CA1 are in default mode. Write (B8h), Read (B9h)
2.9.3 VBUS Access
The TVP5160 decoder has additional internal registers accessible through an indirect access to an
internal 24-bit address wide VBUS. Figure 2-13 shows the VBUS registers access.
2
I C Registers
VBUS Registers
00h
00 0000h
Host
2
80 051Ch
80 0520h
80 052Ch
80 0600h
I C
CC
WSS/CGMS
VITC
Processor
E0h
VBUS
Data
Line Mode
E1h
E8h
VBUS[23:0]
80 0700h
90 1904h
VPS/Gemstar
FIFO
VBUS
Address
EAh
FFh
FF FFFFh
Figure 2-13. VBUS Access
Copyright © 2005–2011, Texas Instruments Incorporated
Functional Description
33
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