TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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0
SCLK
Y[9:0]
Y
Y
Y
Y
Horizontal Blanking
Horizontal Blanking
Y0
Y1
Y2
Y3
CbCr[9:0]
Cb
Cr
Cb
Cr
Cb0 Cr0 Cb1 Cr1
HS Start
HS Stop
HS
A
C
B
D
AVID
AVID Stop
AVID Start
NOTE: AVID rising edge occurs 4 clock cycles early.
NOTE: AVID rising edge occurs 4 clock cycles early.
Figure 2-10. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
SCLK = 1X PIXEL CLOCK(1)
MODE
NTSC 601
A
B
C
D
53
56
53
56
64
64
64
64
19
22
19
22
138
144
138
144
PAL 601
480p
576p
(1) 20-bit 4:2:2 timing with 1× pixel clock reference 601 = ITU-R BT.601 timing
30
Functional Description
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