TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
HS
First Field
B/2
B/2
VS
HS
H/2 + B/2
H/2 + B/2
Second Field
VS
Figure 2-11. VS Position With Respect to HS for Interlaced Signals
HS
B/2
B/2
VS
Figure 2-12. VS Position With Respect to HS for Progressive Signals
10-BIT (SCLK = 2× PIXEL CLOCK) 20-BIT (SCLK = 1× PIXEL CLOCK)
MODE(1)
B/2
64
H/2
858
864
858
864
B/2
32
32
32
32
H/2
429
432
NTSC 601 interlaced
PAL 601 interlaced
NTSC 601 progressive
PAL 601 progressive
64
(1) 601 = ITU-R BT.601 timing
2.8 Embedded Syncs
Standard with embedded syncs insert SAV and EAV codes into the data stream on the rising and falling
edges of AVID. These codes contain the V and F bits which also define vertical timing. Table 2-6 shows
the format of the SAV and EAV codes.
H equals 1b always indicates EAV. H equals 0b always indicates SAV. The alignment of V and F to the
line and field counter varies depending on the standard.
The P bits are protection bits:
•
•
•
•
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Copyright © 2005–2011, Texas Instruments Incorporated
Functional Description
31
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