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TVP5160PNP 参数 Datasheet PDF下载

TVP5160PNP图片预览
型号: TVP5160PNP
PDF下载: 下载PDF文件 查看货源
内容描述: NTSC / PAL / SECAM /组件2×10位数字视频解码器 [NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder]
分类和应用: 解码器
文件页数/大小: 111 页 / 1417 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TVP5160  
SLES135EFEBRUARY 2005REVISED APRIL 2011  
www.ti.com  
Table 2-6. EAV and SAV Sequence  
Y9 (MSB)  
Y8  
1
Y7  
1
Y6  
1
Y5  
1
Y4  
1
Y3  
1
Y2  
1
Y1  
1
Y0  
1
Preamble  
Preamble  
Preamble  
Status  
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
V
H
P3  
P2  
P1  
P0  
0
0
2.9 I2C Host Interface  
Communication with the TVP5160 decoder is via an I2C host interface. The I2C standard consists of two  
signals, the serial input/output data (SDA) line and input/output clock line (SCL), which carry information  
between the devices connected to the bus. A 2-bit control signal (I2CA0/ I2CA1) selects the slave  
address. Although an I2C system can be multi-mastered, the TVP5160 decoder can function as a slave  
device only. Because SDA and SCL are kept open-drain at logic high output level or when the bus is not  
driven, the user must connect SDA and SCL to IOVDD via a pullup resistor on the board. The slave  
address select, terminals 83 and 82 (I2CA0 and I2CA1), enables the use of four TVP5160 devices tied to  
the same I2C bus, because it controls the two least significant bits of the I2C device address.  
Table 2-7. I2C Host Interface Terminal Description  
SIGNAL  
I2CA0  
I2CA1  
SCL  
TYPE  
DESCRIPTION  
Slave address selection  
Slave address selection  
Input clock line  
I
I
I/O  
I/O  
SDA  
Input/output data line  
2.9.1 Reset and I2C Bus Address Selection  
The TVP5160 decoder can respond to four possible chip addresses. The address selection is made at  
reset by an externally supplied level on the I2CA0/I2CA1 pins. The TVP5160 decoder samples the level of  
terminals 83 and 82 at power up or at the trailing edge of RESETB and configures the I2C bus address bit  
A0/A1.  
Table 2-8. I2C Host Interface Device Addresses  
A6  
1
A5  
0
A4  
1
A3  
1
A2  
1
A1(I2CA1)(1)  
A0 (I2CA0)(1)  
R/W  
1/0  
1/0  
1/0  
1/0  
HEX  
0 (default)  
0 (default)  
B9/B8  
BB/BA  
BD/BC  
BF/BE  
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
(1) To pull up the I2C terminals high, tie to IOVDD via a 2.2-kΩ resistor.  
32  
Functional Description  
Copyright © 20052011, Texas Instruments Incorporated  
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