TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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IDID1:
Bit 0/1 – Transaction video line number [9:8]
Bit 2 – Match 2 flag
Bit 3 – Match 1 flag
Bit 4 – 1b if at least one error was detected in the EDC block. 0b if no error was detected.
CS:
Sum of Y7–Y0 of byte 8 through byte 4N+5. For teletext modes, byte 8 is the sync pattern
byte. Byte 9 is Sample 1.
Fill byte:
Fill byte makes a multiple of 4 bytes from byte zero to last fill byte
2.10.2 VBI Raw Data Out
The TVP5160 decoder can output raw A/D video data at twice the sampling rate for external VBI slicing.
This is transmitted as an ancillary data block, although a bit differently from the way the sliced VBI data is
transmitted in the FIFO format as described in Section 3.10.1. The samples are transmitted during the
active portion of the line. VBI raw data uses ITU-R BT 656 format having only luma data. The chroma
samples are replaced by luma samples. The TVP5160 decoder inserts a 4-byte preamble 000h 3FFh
3FFh 180h before data start. There is no checksum byte or fill bytes in this mode.
DATA
NO.
Y9
(MSB)
Y0
(LSB)
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
DESCRIPTION
0
1
2
3
4
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VBI raw data preamble
Sample 1
2× pixel rate
Luma data
(i.e., NTSC 601: n = 1707)
5
⋮
Sample 2
⋮
n–1
N
Sample n–5
Sample n–4
2.11 Powerup, Reset, and Initialization
No specific power-up sequence is required, but all power supplies must be active and stable within 500
ms of each other. Reset may be low during power-up, but must remain low for at least 1 µs after the
power supplies become stable and the crystal begins to oscillate. Alternately, reset may be asserted any
time after power up and a stable crystal oscillation, and must remain asserted for at least 1 µs. Table 2-11
describes the status of the TVP5160 terminals during and immediately after reset.
200 µs must be allowed after reset before commencing I2C operations if the SCL pin is not monitored
during I2C operations
Table 2-11. Reset Sequence
SIGNAL NAME
Y[9:0], SCLK
C[9:0]/GPIO
DURING RESET
RESET COMPLETED
High-impedance
Input
Input
Input
Input
RESETB, PWDN, SDA, SCL, FSS/GPIO,
AVID/GPIO, GLCO/GPIO/I2CA0, HS/CS/GPIO,
VS/VBLK/GPIO, FID/GPIO
Input
INTREQ
Input
Output (open drain)
36
Functional Description
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