TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
0
SCLK
EAV EAV EAV EAV
SAV SAV SAV SAV
Y[9:0]
Cb
Y
Cr
Y
Horizontal Blanking
Cb0
Y0
Cr0
Y1
1
2
3
4
1
2
3
4
HS Start
HS Stop
HS
A
C
B
D
AVID
AVID Stop
AVID Start
Figure 2-9. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
SCLK = 2× PIXEL CLOCK(1)
MODE
A
B
C
D
NTSC 601
PAL 601
480p
106
112
106
112
128
128
128
128
42
48
42
48
276
288
276
288
576p
(1) ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference 601 = ITU-R BT.601 timing
Copyright © 2005–2011, Texas Instruments Incorporated
Functional Description
29
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