TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
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SWCS046N –MARCH 2010–REVISED APRIL 2012
Bits
7
Field Name
RESERVED
I2CCTLP
Description
Type
RW
Reset
Reserved bit
1
0
6
SDACTL and SCLCTL pull-up control:
1: Pull-up is enabled
RW
0: Pull-up is disabled
5
4
3
2
1
0
I2CSRP
SDASR and SCLSR pull-up control:
1: Pull-up is enabled
0: Pull-up is disabled
RW
RW
RW
RW
RW
RW
0
1
1
1
1
1
PWRONP
SLEEPP
PWRON pad pull-up control:
1: Pull-up is enabled
0: Pull-up is disabled
SLEEP pad pull-down control:
1: Pull-down is enabled
0: Pull-down is disabled
PWRHOLDP
BOOT1P
BOOT0P
PWRHOLD pad pull-down control:
1: Pull-down is enabled
0: Pull-down is disabled
BOOT1 pad control:
1: Pull-down is enabled
0: Pull-down is disabled
BOOT0 pad control:
1: Pull-down is enabled
0: Pull-down is disabled
Table 41. REF_REG
Address Offset
Physical Address
Description
Type
0x1D
Instance
Reference control register
RW
7
6
5
4
3
2
1
0
Reserved
VMBCH_SEL
ST
Bits
Field Name
Description
Type
Reset
7:4
Reserved
Reserved bit
RO
R returns
0s
0x0
3:2
1:0
VMBCH_SEL
Main Battery comparator VMBCH programmable threshold (EEPROM
bits):
VMBCH_SEL[1:0] = 00 : bypass
VMBCH_SEL[1:0] = 01 : VMBCH = 2.8 V
VMBCH_SEL[1:0] = 10 : VMBCH = 2.9 V
VMBCH_SEL[1:0] = 11 : VMBCH = 3.0 V
RW
0x0
0x1
ST
Reference state:
RO
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Reserved
ST[1:0] = 11 : On low power (SLEEP)
(Write access available in test mode only)
Table 42. VRTC_REG
Address Offset
Physical Address
Description
Type
0x1E
Instance
VRTC internal regulator control register
RW
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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