TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
SWCS046N –MARCH 2010–REVISED APRIL 2012
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Bits
Field Name
Description
Type
Reset
3
IT_ALARM
Enable one interrupt when the alarm value is reached (TC ALARM
registers) by the TC registers
RW
0
2
IT_TIMER
EVERY
Enable periodic interrupt
0: interrupt disabled
1: interrupt enabled
RW
RW
0
1:0
Interrupt period
00: every second
01: every minute
10: every hour
11: every day
0x0
Table 31. RTC_COMP_LSB_REG
Address Offset
Physical Address
Description
0x13
Instance
RTC compensation register (LSB)
Notes: This register must be written in 2-complement.
This means that to add one 32kHz oscillator period every hour, micro-controller needs to write FFFF into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period every hour, micro-controller needs to write 0001 into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type
RW
7
6
5
4
3
2
1
0
RTC_COMP_LSB
Bits
Field Name
Description
Type
Reset
7:0
RTC_COMP_LSB
This register contains the number of 32-kHz periods to be added into the
32-kHz counter every hour [LSB]
RW
0x00
Table 32. RTC_COMP_MSB_REG
Address Offset
Physical Address
Description
0x14
Instance
RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type
RW
7
6
5
4
3
2
1
0
RTC_COMP_MSB
Bits
Field Name
Description
Type
Reset
7:0
RTC_COMP_MSB
This register contains the number of 32-kHz periods to be added into the
32-kHz counter every hour [MSB]
RW
0x00
Table 33. RTC_RES_PROG_REG
Address Offset
Physical Address
Description
Type
0x15
Instance
RTC register containing oscillator resistance value
RW
7
6
5
4
3
2
1
0
Reserved
SW_RES_PROG
60
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TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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