TPS55340
SLVSBD4 –MAY 2012
www.ti.com
1
CFF
=
VREF
VOUT
2p´R1´ ¦ZFF
´
(37)
where RESR is the ESR of the output capacitor.
If a network measurement tool is available, the most accurate compensation design can be achieved following
this procedure. The power stage frequency response is first measured using a network analyzer at the minimum
5 V input and maximum 800 mA load. This measurement is shown in Figure 16. In this design only one pole and
one zero are used, so the maximum phase increase from the compensation will be 180 degrees. For a 60
degree phase margin, the power stage phase must be –120 degrees at its lowest point. Based on the target
6 kHz bandwidth, the measured power stage gain, KPS(fBW), is 24.84 dB and the phase is –110.3 degrees.
60
0
Gain
Phase
40
−30
−60
−90
−120
−150
−180
20
0
−20
−40
−60
100
1k
10k
100k
Frequency (Hz)
G016
Figure 16. Power Stage Gain and Phase of the Boost Converter
R3 is then chosen to set the compensation gain to be the reciprocal of the power stage gain at the target
bandwidth using Equation 38. C4 is then chosen to place a zero at 1/10 the target bandwidth with Equation 39.
In this case R3 is calculated to be 2.56 kΩ, the nearest standard value 2.55 kΩ is used. C4 is calculated at
0.104 µF and the nearest standard value 0.100 µF is used. Although not necessary because this design uses all
ceramic capacitors, a 100 pF capacitor is selected for C5 to add a high frequency pole at a frequency 100 times
the target bandwidth.
1
R3 =
K
¦
(
æ
ç
) ö
÷
PS BW
20
R1
Gea´
´10
ç
ç
÷
÷
R1+ R2
(
)
è
ø
(38)
(39)
1
C4 =
¦
BW
2p´R3´
10
18
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