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TPS54310-EP 参数 Datasheet PDF下载

TPS54310-EP图片预览
型号: TPS54310-EP
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V至6 V的输入, 3 -A输出,具有集成FET的同步降压PWM切换器( SWIFT ™ ) [3-V TO 6-V INPUT, 3-A OUTPUT,SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs(SWIFT™)]
分类和应用: 输出元件输入元件
文件页数/大小: 21 页 / 750 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SLVS818 – APRIL 2008
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www.ti.com
APPLICATION INFORMATION
shows the schematic diagram for a typical TPS54310 application. The TPS54310 (U1) can provide up
to 3 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the thermal pad
under the TPS54310 integrated circuit needs to be soldered well to the printed-circuit board.
J1
V
I
GND
VIN
2
1
C2
1
R1
10 kΩ
+
R3
71.5 kΩ
20
19
18
17
C3
0.1
µF
PWRGD
U1
TPS54310PWP
RT
SYNC
SS/ENA
VIN
VIN
VIN
PH
PH
16
15
14
10
9
+
C9
180
µF
4V
C7
0.047
µF
C11
1000 pF
L1
1.2
µH
1
2
J3
V
O
GND
C8
10
µF
VBIAS
4
PWRGD
3 COMP
C4
100 pF
C5
3900 pF
R2
3.74 kΩ
8
PH
7
PH
6
PH
2
VSENSE
5
BOOT
13
PGND
1
AGND
12
PGND
11
PGND
PwrPAD
C6
R4
3.74 kΩ
1
Optional
2700 pF
R5
R6
732
R7
49.9
10 kΩ
Figure 10. TPS54310 Schematic
INPUT VOLTAGE
The input to the circuit is a nominal 5 VDC, applied at
J1. The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of
3 A. C8 is the decoupling capacitor for the TPS54310
and must be located as close to the device as
possible.
SETTING THE OUTPUT VOLTAGE
The output voltage of the TPS54310 can be set by
feeding back a portion of the output to the VSENSE
pin using a resistor divider network. In the application
circuit of
this divider network is comprised
of resistors R5 and R4. To calculate the resistor
values to generate the required output voltage use
R5 x 0.891
R4 =
V
O
- 0.891
(1)
Start with a fixed value of R5 and calculate the
required R4 value. Assuming a fixed value of 10 kΩ
for R5, the following table gives the appropriate R4
value for several common output voltages:
OUTPUT VOLTAGE (V)
1.2
1.5
1.8
2.5
3.3
R4 VALUE (KΩ)
28.7
14.7
9.76
5.49
3.74
FEEDBACK CIRCUIT
The resistor divider network of R5 and R4 sets the
output voltage for the circuit at 3.3 V. R5, along with
R2, R6, C4, C5, and C6 forms the loop compensation
network for the circuit. For this design, a Type 3
topology is used.
8
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