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SLVS818 – APRIL 2008
OPERATING FREQUENCY
In the application circuit, the 350-kHz operation is
selected by leaving RT and SYNC open. Connecting
a 68-kΩ to 180-kΩ resistor between RT (pin 20) and
analog ground can be used to set the switching
frequency from 280 kHz to 700 kHz. To calculate the
RT resistor, use the
R
+
100 kW 500 kHz
ƒ
SW
(2)
OUTPUT FILTER
The output filter is composed of a 1.2-µH inductor
and 180-µF capacitor. The inductor is a low dc
resistance (0.017
Ω)
type, Coilcraft DO1813P-122HC.
The capacitor used is a 4-V special polymer type with
a maximum ESR of 0.015
Ω.
The feedback loop is
compensated so that the unity gain frequency is
approximately 75 kHz.
There should be an area of ground one the top layer
directly under the IC, with an exposed area for
connection to the PowerPAD. Use vias to connect
this ground area to any internal ground planes. Use
additional vias at the ground side of the input and
output filter capacitors as well. The AGND and PGND
pins should be tied to the PCB ground by connecting
them to the ground area under the device as shown.
The only components that should tie directly to the
power ground plane are the input capacitors, the
output capacitors, the input voltage decoupling
capacitor, and the PGND pins of the TPS54310. Use
a separate wide trace for the analog ground signal
path. This analog ground should be used for the
voltage set point divider, timing resistor RT, slow start
capacitor and bias capacitor grounds. Connect this
trace directly to AGND (pin 1).
The PH pins should be tied together and routed to
the output inductor. Since the PH connection is the
switching node, inductor should be located very close
to the PH pins and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot capacitor
close to the IC and minimize the conductor trace
lengths.
Connect the output filter capacitor(s) as shown
between the VOUT trace and PGND. It is important to
keep the loop formed by the PH pins, Lout, Cout and
PGND as small as practical.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
the size of the IC package and the device pinout,
they will have to be routed somewhat close, but
maintain as much separation as possible while still
keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to
analog ground using the isolated analog ground
trace. If a slow-start capacitor or RT resistor is used,
or if the SYNC pin is used to select 350-kHz
operating frequency, connect them to this trace as
well.
PCB LAYOUT
shows a generalized PCB layout guide for
the TPS54310.
The VIN pins should be connected together on the
printed circuit board (PCB) and bypassed with a low
ESR ceramic bypass capacitor. Care should be taken
to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the
TPS54X10 ground pins. The minimum recommended
bypass capacitance is 10-µF ceramic with a X5R or
X7R dielectric and the optimum placement is closest
to the VIN pins and the PGND pins.
The TPS54310 has two internal grounds (analog and
power). Inside the TPS54310, the analog ground ties
to all of the noise sensitive signals, while the power
ground ties to the noisier power signals. Noise
injected between the two grounds can degrade the
performance of the TPS54310, particularly at higher
output currents. Ground noise on an analog ground
plane can also cause problems with some of the
control and bias signals. For these reasons, separate
analog and power ground traces are recommended.
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