TPS54310-EP
SLVS818–APRIL 2008 ..................................................................................................................................................................................................... www.ti.com
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
SYNC
SS/ENA
VBIAS
VIN
SLOW START
CAPACITOR
VSENSE
COMP
COMPENSATION
NETWORK
PWRGD
BOOT
BIAS CAPACITOR
EXPOSED
POWERPAD
AREA
BOOT
CAPACITOR
Vin
VIN
PH
PH
PH
PH
PH
VOUT
VIN
PGND
PGND
PGND
OUTPUT INDUCTOR
PH
INPUT
BYPASS
INPUT
BULK
CAPACITOR
FILTER
OUTPUT
FILTER
CAPACITOR
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 11. TPS54310 PCB Layout
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog
ground plane must provide adequate heat dissipating
area. A 3 inch by 3 inch plane of 1 ounce copper is
recommended, though not mandatory, depending on
ambient temperature and airflow. Most applications
have larger areas of internal ground plane available,
and the PowerPAD should be connected to the
largest area available. Additional areas on the top or
bottom layers also help dissipate heat, and any area
available should be used when 3 A or greater
operation is desired. Connection from the exposed
area of the PowerPAD to the analog ground plane
layer should be made using 0.013 inch diameter vias
to avoid solder wicking through the vias. Six vias
should be in the PowerPAD area with four additional
vias located under the device package. The size of
the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018.
Additional vias beyond the ten recommended that
enhance thermal performance should be included in
areas not under the device package.
10
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS54310-EP
TI [ TEXAS INSTRUMENTS ]
