TPS5430-Q1
SLVS751C–NOVEMBER 2007–REVISED JULY 2009................................................................................................................................................... www.ti.com
PIN ASSIGNMENTS
DDA PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
BOOT
NC
PH
VIN
NC
GND
ENA
VSENSE
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
BOOT
NC
NO.
1
Boost capacitor for the high-side FET gate driver. Connect 0.01-µF low ESR capacitor from BOOT pin to PH pin.
Not connected internally
2, 3
4
VSENSE
ENA
Feedback voltage for the regulator. Connect to output voltage divider.
On/off control. Below 0.5 V, the device stops switching. Float the pin to enable.
Ground. Connect to thermal pad.
5
GND
6
Input supply voltage. Bypass VIN pin to GND pin close to device package with a high-quality low-ESR ceramic
capacitor.
VIN
7
PH
8
9
Source of the high side power MOSFET. Connected to external inductor and diode.
GND pin must be connected to the exposed pad for proper operation.
PowerPAD
4
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Product Folder Link(s): TPS5430-Q1
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