SLVS751C – NOVEMBER 2007 – REVISED JULY 2009
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ENA has an internal pullup current source, allowing the user to float the ENA pin. If an application requires
controlling ENA, use open-drain or open-collector output logic to interface with the pin. To limit the start-up inrush
current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its final value, linearly.
The internal slow start time is 8 ms typically.
Undervoltage Lockout (UVLO)
The TPS5430 incorporates a UVLO circuit to keep the device disabled when VIN (the input voltage) is below the
UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is
grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached,
the internal slow start is released and device start-up begins. The device operates until VIN falls below the UVLO
stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.
Boost Capacitor (BOOT)
Connect a 0.01-µF low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the
gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable
values over temperature.
Output Feedback (VSENSE) and Internal Compensation
The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider
network to the VSENSE pin. In steady-state operation, VSENSE voltage should be equal to the voltage
reference, 1.221 V.
The TPS5430 implements internal compensation to simplify the regulator design. Since the TPS5430 uses
voltage-mode control, a type-3 compensation network has been designed on chip to provide a high crossover
frequency and a high phase margin for good stability. See
Internal Compensation Network
in the
Advanced
Information
section for more details.
Voltage Feed Forward
The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input
voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward
varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are
constant at the feed forward gain, i.e,:
VIN
Feed Forward Gain
+
Ramp
pk*pk
(1)
The typical feed-forward gain of the TPS5430 is 25.
Pulse-Width Modulation (PWM) Control
The regulator employs a fixed-frequency PWM control method. First, the feedback voltage (VSENSE pin voltage)
is compared to the constant voltage reference by the high-gain error amplifier and compensation network to
produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this
way, the error voltage magnitude is converted to a pulse width, which is the duty cycle. Finally, the PWM output
is fed into the gate-drive circuit to control the on time of the high-side MOSFET.
Overcurrent Limiting
Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The
drain-to-source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the
drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system
ignores the overcurrent indicator for the leading-edge blanking time at the beginning of each cycle to avoid any
turn-on noise glitches.
Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for
the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current
limiting.
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