TPS40210-Q1, TPS40211-Q1
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SLVS861D –AUGUST 2008–REVISED APRIL 2010
IL ripple
(
)
1.02A
CIN
>
=
= 7.0mF
4´ V
´ fSW
4´ 60mV ´ 600kHz
IN ripple
(
)
(47)
(48)
V
IN ripple
(
)
60mV
ESR <
=
= 30mW
2´IL ripple
2´1.02A
(
)
For this design, to meet a maximum input ripple of 60 mV, a minimum 7.0-mF input capacitor with ESR less than
30 mΩ is needed. A 10-mF X7R ceramic capacitor is selected.
Current Sense and Current Limit
The maximum allowable current sense resistor value is limited by both the current limit and sub-harmonic
stability. These two limitations are given by Equation 49 and Equation 50.
VOCP(min)
110mV
RISNS
<
=
= 14.2mW
1.1´ 6.57A + 0.50A
1.1´ I
+IDrive
)
(
L peak
VDD
(
)
(49)
(50)
´L ´ f
14V ´10mH´ 600kHz
MAX
SW
R
<
=
= 133mW
ISNS
60´(V
+ V - V ) 60´(24V + 0.48V -14V)
OUT
fd
IN
The current limit requires a resistor less than 14.2 mΩ, and stability requires a sense resistor less than 133 mΩ.
A 10-mΩ resistor is selected. Approximately 2-mΩ of routing resistance is added in compensation calculations.
Current Sense Filter
To remove switching noise from the current sense, an R-C filter is placed between the current sense resistor and
the ISNS pin. A resistor with a value between 1 kΩ and 5 kΩ is selected, and a capacitor value is calculated by
Equation 51.
0.1´D
0.1´0.428
MIN
C
=
=
= 71pF
IFLT
f
´R
600kHz ´1kW
SW
IFLT
(51)
For a 1-kΩ filter resistor, 71 pF is calculated and a 100-pF capacitor is selected.
Switching MOSFET Selection
The TPS40210 drives a ground referenced N-channel FET. The RDS(on) and gate charge are estimated based on
the desired efficiency target.
æ
ç
è
ö
æ
ç
è
ö
1
1
1
æ
ö
PDISS(total) » POUT
´
-1 = VOUT ´IOUT
´
-1 = 24V ´ 2A ´
-1 = 2.526W
÷
÷
ç
÷
h
h
0.95
è
ø
ø
ø
(52)
For a target of 95% efficiency with a 24-V input voltage at 2 A, maximum power dissipation is limited to 2.526 W.
The main power dissipating devices are the MOSFET, inductor, diode, current sense resistor and the integrated
circuit, the TPS40210.
P
< PDISS total - P - PD - PRisns - VIN(max) ´IVDD
L
FET
(
)
(53)
This leaves 740 mW of power dissipation for the MOSFET. This can likely cause an SO-8 MOSFET to get too
hot, so power dissipation is limited to 500 mW. Allowing half for conduction and half for switching losses, we can
determine a target RDS(on) and QGS for the MOSFET by Equation 54 and Equation 55.
3´P
´I
3´ 0.50W ´0.50A
FET DRIVE
Q
<
=
= 13.0nC
GS
2´ V
´I
´ f
2´ 24V ´ 2A ´ 600kHz
OUT OUT
SW
(54)
A target MOSFET gate-to-source charge of less than 13.0 nC is calculated to limit the switching losses to less
than 250 mW.
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