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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
6.9.4
Low-Power Mode Wakeup Timing
shows the timing requirements,
shows the switching characteristics, and
shows the timing diagram for IDLE mode.
Table 6-16. IDLE Mode Timing Requirements
(1)
MIN
NOM
MAX
UNIT
cycles
Without input qualifier
With input qualifier
2t
c(SCO)
5t
c(SCO)
+ t
w(IQSW)
t
w(WAKE-INT)
(1)
Pulse duration, external wake-up signal
For an explanation of the input qualifier parameters, see
Table 6-17. IDLE Mode Switching Characteristics
(1)
PARAMETER
Delay time, external wake signal to
program execution resume
(2)
•
t
d(WAKE-IDLE)
•
•
(1)
(2)
Wake-up from Flash
– Flash module in active state
Wake-up from Flash
– Flash module in sleep state
Wake-up from SARAM
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20t
c(SCO)
20t
c(SCO)
+ t
w(IQSW)
1050t
c(SCO)
1050t
c(SCO)
+ t
w(IQSW)
20t
c(SCO)
20t
c(SCO)
+ t
w(IQSW)
cycles
cycles
cycles
TEST CONDITIONS
MIN
TYP
MAX
UNIT
For an explanation of the input qualifier parameters, see
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
WAKE INT
(A)
A.
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-14. IDLE Entry and Exit Timing
Copyright © 2003–2011, Texas Instruments Incorporated
Electrical Specifications
113
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