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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
Table 6-13. Reset (XRS) Timing Requirements
MIN
t
w(RSL1)
t
w(RSL2)
t
w(WDRS)
t
d(EX)
t
OSCST
(1)
(2)
(2)
(1)
NOM
MAX
UNIT
cycles
cycles
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Pulse duration, reset pulse generated by
watchdog
Delay time, address/data valid after XRS high
Oscillator start-up time
Hold time for boot-mode pins
Warm reset
8t
c(OSCCLK)
8t
c(OSCCLK)
512t
c(OSCCLK)
32t
c(OSCCLK)
1
200t
c(OSCCLK)
10
cycles
cycles
ms
cycles
t
h(boot-mode)
In addition to the t
w(RSL1)
requirement, XRS has to be low at least for 1 ms after V
DD
reaches 1.5 V.
Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
XCLKOUT
OSCCLK * 5
t
w(RSL2)
XRS
Address/Data/
Control
(Internal)
Boot-Mode
Pins
t
d(EX)
User-Code Execution
(Don’t Care)
OSCCLK/8
User-Code Dependent
User-Code Execution Phase
Boot-ROM Execution Starts
Peripheral/GPIO Function
GPIO Pins as Input
t
h(boot-mode)(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-9. Warm Reset
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Electrical Specifications
109
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