SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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Table 6-18. STANDBY Mode Timing Requirements
TEST CONDITIONS
t
w(WAKE-INT)
(1)
Pulse duration, external
wake-up signal
Without input qualification
With input qualification
(1)
MIN
3t
c(OSCCLK)
(2 + QUALSTDBY) * t
c(OSCCLK)
NOM
MAX
UNIT
cycles
QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-19. STANDBY Mode Switching Characteristics
PARAMETER
t
d(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low
Delay time, external wake signal
to program execution resume
(1)
•
Wake up from flash
– Flash module in active
state
Wake up from flash
– Flash module in sleep
state
Wake up from SARAM
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
•
(1)
With input qualifier
100t
c(SCO)
100t
c(SCO)
+ t
w(WAKE-INT)
1125t
c(SCO)
1125t
c(SCO)
+ t
w(WAKE-INT)
100t
c(SCO)
100t
c(SCO)
+ t
w(WAKE-INT)
cycles
cycles
TEST CONDITIONS
MIN
32t
c(SCO)
TYP
MAX
45t
c(SCO)
UNIT
cycles
t
d(WAKE-STBY)
•
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(B)
Device
Status
Flushing Pipeline
Wake−up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
STANDBY
(C)
(D)
STANDBY
(E)
(F)
Normal Execution
XCLKOUT
t
d(IDLE−XCOL)
A.
B.
IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0)
or 64 cycles (if CLKINDIV = 1) before being turned off. This delay enables the CPU pipe and any other pending
operations to flush properly.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
The external wake-up signal is driven active.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).
C.
D.
E.
F.
Figure 6-15. STANDBY Entry and Exit Timing Diagram
114
Electrical Specifications
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