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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
Table 6-20. HALT Mode Timing Requirements
MIN
t
w(WAKE-GPIO)
t
w(WAKE-XRS)
(1)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
t
oscst
+ 2t
c(OSCCLK)
(1)
NOM
MAX
UNIT
cycles
cycles
t
oscst
+ 8t
c(OSCCLK)
See
for an explanation of t
oscst
.
Table 6-21. HALT Mode Switching Characteristics
PARAMETER
t
d(IDLE-XCOL)
t
p
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
Delay time, PLL lock to program execution resume
•
Wake up from flash
– Flash module in sleep state
•
Wake up from SARAM
MIN
32t
c(SCO)
TYP
MAX
45t
c(SCO)
131072t
c(OSCCLK)
1125t
c(SCO)
35t
c(SCO)
UNIT
cycles
cycles
cycles
cycles
t
d(WAKE-HALT)
(A)
(B)
Device
Status
Flushing Pipeline
(C)
(D)
HALT
HALT
PLL Lock-up Time
Wake-up Latency
(E)
(F)
(G)
Normal
Execution
GPIOn
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A.
B.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0) or
64 cycles (if CLKINDIV = 1) before the oscillator is turned off and the CLKIN to the core is stopped. This delay
enables the CPU pipe and any other pending operations to flush properly.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles. Note that these 131,072 clock cycles are applicable even when the PLL is disabled (i.e., code
execution will be delayed by this duration even when the PLL is disabled).
Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the
interrupt (if enabled), after a latency.
Normal operation resumes.
t
p
C.
D.
E.
F.
G.
Figure 6-16. HALT Wake-Up Using GPIOn
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Electrical Specifications
115
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