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TMS320F28335ZHHA 参数 Datasheet PDF下载

TMS320F28335ZHHA图片预览
型号: TMS320F28335ZHHA
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
www.ti.com  
SPRS439IJUNE 2007REVISED MARCH 2011  
6.6 Timing Parameter Symbology  
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the  
symbols, some of the pin names and other related terminology have been abbreviated as follows:  
Lowercase subscripts and their  
meanings:  
Letters and symbols and their  
meanings:  
a
c
d
access time  
H
L
High  
Low  
cycle time (period)  
delay time  
V
Valid  
Unknown, changing, or don't care  
level  
f
fall time  
X
Z
h
r
hold time  
High impedance  
rise time  
su  
t
setup time  
transition time  
valid time  
v
w
pulse duration (width)  
6.6.1 General Notes on Timing Parameters  
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that  
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.  
The signal combinations shown in the following timing diagrams may not necessarily represent actual  
cycles. For actual cycle examples, see the appropriate cycle description section of this document.  
6.6.2 Test Load Circuit  
This test load circuit is used to measure all switching characteristics provided in this document.  
Tester Pin Electronics  
Data Sheet Timing Reference Point  
Output  
Under  
Test  
42 Ω  
3.5 nH  
Transmission Line  
(Α)  
Z0 = 50 Ω  
(B)  
Device Pin  
4.0 pF  
1.85 pF  
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the  
device pin.  
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its  
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to  
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to  
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.  
Figure 6-4. 3.3-V Test Load Circuit  
Copyright © 2007–2011, Texas Instruments Incorporated  
Electrical Specifications  
125  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232  
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