TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
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Table 8-3. EDMA3 Registers (continued)
HEX ADDRESS
02A0 036C
02A0 0370
02A0 0374
02A0 0378
02A0 037C
02A0 0380
02A0 0384
02A0 0388
02A0 038C
02A0 0390
02A0 0394
02A0 0398
02A0 039C
02A0 0400
02A0 0404
02A0 0408
02A0 040C
02A0 0410
02A0 0414
02A0 0418
02A0 041C
02A0 0420
02A0 0424
02A0 0428
02A0 042C
02A0 0430
02A0 0434
02A0 0438
02A0 043C
02A0 0440
02A0 0444
02A0 0448
02A0 044C
02A0 0450
02A0 0454
02A0 0458
02A0 045C
02A0 0460
02A0 0464
02A0 0468
02A0 046C
02A0 0470
02A0 0474
02A0 0478
02A0 047C
02A0 0480
02A0 0484
ACRONYM
REGISTER NAME
DRAEH5
DRAE6
DRAEH6
DRAE7
DRAEH7
QRAE0
QRAE1
QRAE2
QRAE3
QRAE4
QRAE5
QRAE6
QRAE7
Q0E0
DMA Region Access Enable Register High for Region 5
DMA Region Access Enable Register for Region 6
DMA Region Access Enable Register High for Region 6
DMA Region Access Enable Register for Region 7
DMA Region Access Enable Register High for Region 7
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 4
QDMA Region Access Enable Register for Region 5
QDMA Region Access Enable Register for Region 6
QDMA Region Access Enable Register for Region 7
Event Queue 0 Entry Register 0
Q0E1
Event Queue 0 Entry Register 1
Q0E2
Event Queue 0 Entry Register 2
Q0E3
Event Queue 0 Entry Register 3
Q0E4
Event Queue 0 Entry Register 4
Q0E5
Event Queue 0 Entry Register 5
Q0E6
Event Queue 0 Entry Register 6
Q0E7
Event Queue 0 Entry Register 7
Q0E8
Event Queue 0 Entry Register 8
Q0E9
Event Queue 0 Entry Register 9
Q0E10
Q0E11
Q0E12
Q0E13
Q0E14
Q0E15
Q1E0
Event Queue 0 Entry Register 10
Event Queue 0 Entry Register 11
Event Queue 0 Entry Register 12
Event Queue 0 Entry Register 13
Event Queue 0 Entry Register 14
Event Queue 0 Entry Register 15
Event Queue 1 Entry Register 0
Q1E1
Event Queue 1 Entry Register 1
Q1E2
Event Queue 1 Entry Register 2
Q1E3
Event Queue 1 Entry Register 3
Q1E4
Event Queue 1 Entry Register 4
Q1E5
Event Queue 1 Entry Register 5
Q1E6
Event Queue 1 Entry Register 6
Q1E7
Event Queue 1 Entry Register 7
Q1E8
Event Queue 1 Entry Register 8
Q1E9
Event Queue 1 Entry Register 9
Q1E10
Q1E11
Q1E12
Q1E13
Q1E14
Q1E15
Q2E0
Event Queue 1 Entry Register 10
Event Queue 1 Entry Register 11
Event Queue 1 Entry Register 12
Event Queue 1 Entry Register 13
Event Queue 1 Entry Register 14
Event Queue 1 Entry Register 15
Event Queue 2 Entry Register 0
Q2E1
Event Queue 2 Entry Register 1
84
Peripheral Information and Electrical Specifications
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