TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
1.1 CUN/GUN/ZUN BGA Package (Bottom View)
The devices are designed for a package temperature range of 0°C to 100°C (commercial temperature
range). A heatsink is required so that this range is not exceeded.
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Figure 1-1. CUN/GUN/ZUN 561-Pin BGA Package (Bottom View)
1.2 Description
The TMS320C64x+ DSPs (including the TMS320TCI6487/8 device) are the highest-performance
communications infrastructure DSP generation in the TMS320C6000™ DSP platform. The TCI6487/8
device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word
(VLIW) architecture developed by Texas Instruments (TI), designed specifically for wireless infrastructure
base-band applications makes these DSPs an ideal solution for Pico, Micro, and Macro BTS and enables
SOC base-band solution for UMTS, TD-SCDMA, WiMAX and cdma2000 applications, including video and
telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are
upward code-compatible from previous devices that are part of the C6000™ DSP platform.
1.2.1 Core Processor
Based on 65-nm process technology and 3.0 GHz of total raw DSP processing power with performance of
up to 24,000 million instructions per second (MIPS) [or 24,000 16-bit MMACs per cycle], the TCI6487/8
device offers cost-effective solutions to high-performance DSP programming challenges with three
independent DSP subsystems. The DSP possesses the operational flexibility of high-speed controllers and
numerical capability of array processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these functional units are multipliers or .M units. Each C64x+ .M unit doubles the
multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs)
every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a
1.0-GHz rate, this means 8000 16-bit MMACs can occur every second. Moreover, each multiplier on the
C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.
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Features
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