TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.22.2 FSYNC Electrical Data/Timing
Table 8-81. Timing Requirements for FSYNC
(see Figure 8-44, Figure 8-45, and Figure 8-46)
NO.
1
PARAMETER
MIN
MAX UNIT
tc(FSCLK)
tc(FSCLK)
tu(FSPLS)
th(FSPLS)
Cycle time
8.1388
ns
2
Pulse duration, ALTSYNCCLK high or low
Setup time, ALTFSYNCPULSE high before ALTFSYNCCLK high
Hold time, ALTFSYNCPULSE low after ALTFSYNCCLK high
0.4 tc(FSCLK)
0.6 tc(FSCLK)
ns
ns
ns
3
2
2
4
1
2
2
FSYNCCLK
FRAMEBURST
3
4
Figure 8-44. FSYNC Clock and Synchronization Timing
1
2
2
ALTFSYNCCLK
ALTFSYNCPULSE
3
4
Figure 8-45. Alternate FSYNC Clock and Synchronization Timing
1
2
2
TRTCLK
TRT
3
4
Figure 8-46. TRT Clock and Synchronization Timing
Submit Documentation Feedback
Peripheral Information and Electrical Specifications
199
TI [ TEXAS INSTRUMENTS ]
