TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.22 Frame Synchronization
Frame synchronization handles timing and time alignment on the device by coordinating timing between
the DSP cores. Up to 30 programmable events based on RP3 or system timer. One output is used for
exporting frame alignment to aid in synchronizing external components.
Frame synchronization assists with synchronization of clock inputs:
•
•
•
OBSAI RP1 compliant input for frame burst data.
UMTS frame synchronization boundary used as an alternative to RP1 for frame burst data.
System timer synchronization used as an alternative to RP1.
The user may select between the OBSAI RP1-compliant FSYNCCLK(P|N) and FRAMEBURST(P|N)
signals or the alternate, single-ended ALTFSYNCCLK and ALTFSYNCPULSE inputs to drive the timers.
Table 8-79. FSYNC Event Connections
C64x+
MEGAMODULE
CORE 0
C64x+
MEGAMODULE
CORE 1
C64x+
MEGAMODULE
CORE 2
MODULE EVENTS
CIC0
CIC1
CIC2
TPCC
CIC3
TIMER
AIF
RAC
FSEVT0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FSEVT1
X
FSEVT2
X
X
FSEVT3
FSEVT4
X
X
X
X
X
X
X
X
X
X
X
FSEVT5
FSEVT6
FSEVT7
FSEVT8
FSEVT9
FSEVT10
FSEVT11
FSEVT12
FSEVT13
FSEVT14
FSEVT15
FSEVT16
FSEVT17
FSEVT18
FSEVT19
FSEVT20
FSEVT21
FSEVT22
FSEVT23
FSEVT24
FSEVT25
FSEVT26
FSEVT27
FSEVT28
FSEVT29
FS_ERR_Alarm0
FS_ERR_Alarm1
FS_AIFFrameSync
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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