TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
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SPRS358F–APRIL 2007–REVISED AUGUST 2008
8.23 RAC (TCI6488 Only)
The RAC subsystem is a receive chip rate accelerator based on a generic correlator coprocessor (GCCP).
It supports UMTS operations; assists in transferring data received from the antenna data to the Receive
core and performs receive functions targets at W-CDMA Macro bits.
The RAC subsystem consists of several components:
•
2 GCCP accelerators for Finger Despread (FD), Path Monitor (PM), Preamble Detection (PD), and
Stream Power Estimator (SPE).
•
•
Back-end Interface (BEI) for management of the RAC configuration and the data output.
Front-end Interface (FEI) for reception of the antenna data for processing and access to all memory
mapped registers (MMRs) and memories in the RAC components.
The RAC has a total of 3 ports connected to the DMA crossbar:
•
BEI includes two master connections to the DMA SCR for output data to device memory. One is
128-bit and the other is 64-bit, both are clocked at the same rate as the DMA crossbar.
•
The FEI has a slave connection to the DMA SCR for input data as well as direct memory access (to
facilitate debug).
The RAC has one single 32-bit port running at 1/3 the CPU clock to be used for configuration accesses.
This is connected to the CFG crossbar via a bridge that performs 3:4 clock conversions. All masters have
access to this port.
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Peripheral Information and Electrical Specifications
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