TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
Table 8-78. Antenna Interface System Registers (continued)
HEX ADDRESS
02BF 3158
ACRONYM
REGISTER NAME
EE_EV3_LINK_MSK_CLR_A
EE_EV3_LINK_MSK_CLR_B
EE_COMMON_MSK_CLR_EV3
-
Event 3 Link Interrupt Mask Clear Register A
Event 3 Link Interrupt Mask Clear Register B
02BF 315C
02BF 3160
Event Enable 3 Common Interrupt Mask Clear Register
Reserved
02BF 3164 - 02BF 31FC
02BF 3200
EE_INT_VECT_EV0
EE_INT_VECT_EV1
EE_INT_VECT_EV2
EE_INT_VECT_EV3
-
Event Enable Interrupt Vector Register for AI_EVENT0
Event Enable Interrupt Vector Register for AI_EVENT1
Event Enable Interrupt Vector Register for AI_EVENT2
Event Enable Interrupt Vector Register for AI_EVENT3
Reserved
02BF 3204
02BF 3208
02BF 320C
02BF 3210 - 02BF BFFC
02BF C000
VD_RD_BUSERR
VD_WR_BUSERR
VBUSP DMA Read Bus Interface Status Registers
VBUSP DMA Write Bus Interface Status Registers
02BF C004
8.21.2 Antenna Electrical Data/Timing
The TMS320TCI6488 Hardware Design Guide application report (literature number SPRAAG5) specifies a
complete AIF interface solution for the TCI6487/8 device as well as a list of compatible AIF devices. TI
has performed the simulation and system characterization to ensure all AIF interface timings in this
solution are met; therefore, no electrical data/timing information is supplied here for this interface.
TI only supports designs that follow the board design guidelines outlined in the SPRAAG5
application report.
196
Peripheral Information and Electrical Specifications
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