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TMS320VC5416ZGU160 参数 Datasheet PDF下载

TMS320VC5416ZGU160图片预览
型号: TMS320VC5416ZGU160
PDF下载: 下载PDF文件 查看货源
内容描述: TMS320VC5416定点数字信号处理器 [TMS320VC5416 Fixed-Point Digital Signal Processor]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 98 页 / 855 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320VC5416  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS095OMARCH 1999REVISED JANUARY 2005  
3.12 DMA Controller  
The device direct memory access (DMA) controller transfers data between points in the memory map  
without intervention by the CPU. The DMA allows movements of data to and from internal program/data  
memory, internal peripherals (such as the McBSPs), or external memory devices to occur in the  
background of CPU operation. The DMA has six independent programmable channels, allowing six  
different contexts for DMA operation.  
3.12.1 Features  
The DMA has the following features:  
The DMA operates independently of the CPU.  
The DMA has six channels. The DMA can keep track of the contexts of six independent block  
transfers.  
The DMA has higher priority than the CPU for both internal and external accesses.  
Each channel has independently programmable priorities.  
Each channel's source and destination address registers can have configurable indexes through  
memory on each read and write transfer, respectively. The address may remain constant, be  
post-incremented, be post-decremented, or be adjusted by a programmable value.  
Each read or write internal transfer may be initialized by selected events.  
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.  
The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).  
3.12.2 DMA External Access  
The DMA supports external accesses to data, I/O, and extended program memory. These overlay pages  
are only visible to the DMA controller. A maximum of two DMA channels can be used for external memory  
accesses. The DMA external accesses require a minimum of 8 cycles for external writes and a minimum  
of 11 cycles for external reads assuming the XIO02 is in consecutive mode (CONSEC = 1), wait state is  
set to two, and CLKOUT is not divided (DIVFCT = 00).  
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of  
the external bus, the other will be held-off via wait states until the current transfer is complete. The DMA  
takes precedence over XIO requests.  
Only two channels are available for external accesses. (One for external reads and one for external  
writes.)  
Single-word (16-bit) transfers are supported for external accesses.  
The DMA does not support transfers from the peripherals to external memory.  
The DMA does not support transfers from external memory to the peripherals.  
The DMA does not support external-to-external accesses.  
The DMA does not support synchronized external accesses.  
15  
14  
13  
12  
11  
10  
2
8
0
AUTOINIT  
DINM  
IMOD  
CTMOD  
SLAXS  
SIND  
1
7
6
5
4
DMS  
DLAXS  
DIND  
DMD  
LEGEND: R = Read, W = Write, n = value present after reset  
Figure 3-16. DMA Transfer Mode Control Register (DMMCRn)  
Functional Overview  
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