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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
Contents
Revision History
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2
1
TMS320VC5416 Features
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9
2
Introduction
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2.1
2.2
Description
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Pin Assignments
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2.2.1
Terminal Assignments for the GGU Package
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2.2.2
Pin Assignments for the PGE Package
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2.2.3
Signal Descriptions
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Memory
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3.1.1
Data Memory
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3.1.2
Program Memory
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3.1.3
Extended Program Memory
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On-Chip ROM With Bootloader
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On-Chip RAM
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On-Chip Memory Security
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Memory Map
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3.5.1
Relocatable Interrupt Vector Table
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On-Chip Peripherals
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3.6.1
Software-Programmable Wait-State Generator
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3.6.2
Programmable Bank-Switching
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3.6.3
Bus Holders
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Parallel I/O Ports
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3.7.1
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
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3.7.2
HPI Nonmultiplexed Mode
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Multichannel Buffered Serial Ports (McBSPs)
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Hardware Timer
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Clock Generator
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Enhanced External Parallel Interface (XIO2)
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DMA Controller
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3.12.1 Features
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3.12.2 DMA External Access
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3.12.3 DMA Memory Maps
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3.12.4 DMA Priority Level
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3.12.5 DMA Source/Destination Address Modification
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3.12.6 DMA in Autoinitialization Mode
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3.12.7 DMA Transfer Counting
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3.12.8 DMA Transfer in Doubleword Mode
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3.12.9 DMA Channel Index Registers
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3.12.10 DMA Interrupts
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3.12.11 DMA Controller Synchronization Events
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General-Purpose I/O Pins
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3.13.1 McBSP Pins as General-Purpose I/O
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3.13.2 HPI Data Pins as General-Purpose I/O
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Device ID Register
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Memory-Mapped Registers
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McBSP Control Registers and Subaddresses
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DMA Subbank Addressed Registers
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Interrupts
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Contents
3
3
Functional Overview
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3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
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