TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Contents
Revision History ........................................................................................................................... 2
1
2
TMS320VC5416 Features....................................................................................................... 9
Introduction....................................................................................................................... 10
2.1
Description .................................................................................................................. 10
Pin Assignments............................................................................................................ 10
2.2
2.2.1
2.2.2
2.2.3
Terminal Assignments for the GGU Package ............................................................... 10
Pin Assignments for the PGE Package ...................................................................... 12
Signal Descriptions.............................................................................................. 13
3
Functional Overview ........................................................................................................... 16
3.1
Memory ...................................................................................................................... 16
3.1.1
3.1.2
3.1.3
Data Memory..................................................................................................... 16
Program Memory ................................................................................................ 18
Extended Program Memory ................................................................................... 18
3.2
3.3
3.4
3.5
On-Chip ROM With Bootloader........................................................................................... 18
On-Chip RAM............................................................................................................... 19
On-Chip Memory Security................................................................................................. 19
Memory Map ................................................................................................................ 20
3.5.1
Relocatable Interrupt Vector Table............................................................................ 21
3.6
On-Chip Peripherals ....................................................................................................... 23
3.6.1
3.6.2
3.6.3
Software-Programmable Wait-State Generator ............................................................. 23
Programmable Bank-Switching................................................................................ 25
Bus Holders ...................................................................................................... 26
3.7
Parallel I/O Ports ........................................................................................................... 26
3.7.1
3.7.2
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) .......................................................... 27
HPI Nonmultiplexed Mode...................................................................................... 28
3.8
3.9
Multichannel Buffered Serial Ports (McBSPs).......................................................................... 30
Hardware Timer ............................................................................................................ 32
3.10 Clock Generator ............................................................................................................ 32
3.11 Enhanced External Parallel Interface (XIO2) ........................................................................... 34
3.12 DMA Controller ............................................................................................................. 37
3.12.1 Features .......................................................................................................... 37
3.12.2 DMA External Access........................................................................................... 37
3.12.3 DMA Memory Maps ............................................................................................. 39
3.12.4 DMA Priority Level............................................................................................... 40
3.12.5 DMA Source/Destination Address Modification ............................................................. 40
3.12.6 DMA in Autoinitialization Mode ................................................................................ 41
3.12.7 DMA Transfer Counting......................................................................................... 41
3.12.8 DMA Transfer in Doubleword Mode .......................................................................... 42
3.12.9 DMA Channel Index Registers................................................................................. 42
3.12.10 DMA Interrupts.................................................................................................. 42
3.12.11 DMA Controller Synchronization Events .................................................................... 42
3.13 General-Purpose I/O Pins................................................................................................. 43
3.13.1 McBSP Pins as General-Purpose I/O......................................................................... 43
3.13.2 HPI Data Pins as General-Purpose I/O ...................................................................... 44
3.14 Device ID Register ......................................................................................................... 44
3.15 Memory-Mapped Registers ............................................................................................... 45
3.16 McBSP Control Registers and Subaddresses.......................................................................... 47
3.17 DMA Subbank Addressed Registers .................................................................................... 48
3.18 Interrupts .................................................................................................................... 50
Contents
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