TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
List of Tables
2-1
Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package) ......................................... 11
Signal Descriptions ............................................................................................................... 13
Standard On-Chip ROM Layout ............................................................................................... 19
Processor Mode Status (PMST) Register Bit Fields ........................................................................ 22
Software Wait-State Register (SWWSR) Bit Fields ......................................................................... 24
Software Wait-State Control Register (SWCR) Bit Fields .................................................................. 24
Bank-Switching Control Register (BSCR) Fields.............................................................................. 25
Bus Holder Control Bits .......................................................................................................... 26
Sample Rate Input Clock Selection ........................................................................................... 32
Clock Mode Settings at Reset ................................................................................................. 33
DMD Section of the DMMCRn Register ...................................................................................... 38
DMA Reload Register Selection ............................................................................................... 41
DMA Interrupts ................................................................................................................... 42
DMA Synchronization Events .................................................................................................. 42
DMA Channel Interrupt Selection.............................................................................................. 43
Device ID Register (CSIDR) Bits................................................................................................ 45
CPU Memory-Mapped Registers................................................................................................ 45
Peripheral Memory-Mapped Registers for Each DSP Subsystem ........................................................ 46
McBSP Control Registers and Subaddresses................................................................................. 47
DMA Subbank Addressed Registers ........................................................................................... 48
Interrupt Locations and Priorities................................................................................................ 50
Input Clock Frequency Characteristics......................................................................................... 56
Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options....................................... 57
Divide-By-2 and Divide-By-4 Clock Options Timing Requirements ....................................................... 57
Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics................................................... 57
Multiply-By-N Clock Option Timing Requirements .......................................................................... 59
Multiply-By-N Clock Option Switching Characteristics...................................................................... 59
Memory Read Timing Requirements.......................................................................................... 60
Memory Read Switching Characteristics ..................................................................................... 60
Memory Write Switching Characteristics ..................................................................................... 63
I/O Read Timing Requirements................................................................................................ 64
I/O Read Switching Characteristics ........................................................................................... 64
I/O Write Switching Characteristics............................................................................................ 65
Ready Timing Requirements for Externally Generated Wait States ...................................................... 67
Ready Switching Characteristics for Externally Generated Wait States.................................................. 67
HOLD and HOLDA Timing Requirements.................................................................................... 72
HOLD and HOLDA Switching Characteristics ............................................................................... 72
Reset, BIO, Interrupt, and MP/MC Timing Requirements .................................................................. 74
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics........................... 76
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
List of Tables
7
TI [ TEXAS INSTRUMENTS ]
