TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
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TMS320VC5416 Features
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and One
Program Memory Bus
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Arithmetic Instructions With Parallel Store and
Parallel Load
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Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
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40-Bit Arithmetic Logic Unit (ALU) Including a
40-Bit Barrel Shifter and Two Independent
40-Bit Accumulators
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Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
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On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With External
Clock Source
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Compare, Select, and Store Unit (CSSU) for the
Add/Compare Selection of the Viterbi Operator
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One 16-Bit Timer
Six-Channel Direct Memory Access (DMA)
Controller
Exponent Encoder to Compute an Exponent
Value of a 40-Bit Accumulator Value in a
Single Cycle
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Three Multichannel Buffered Serial Ports
(McBSPs)
8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
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Two Address Generators With Eight Auxiliary
Registers and Two Auxiliary Register
Arithmetic Units (ARAUs)
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Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
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Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
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CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic, IEEE
Std 1149.1 (JTAG) Boundary Scan Logic(1)
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128K x 16-Bit On-Chip RAM Composed of:
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Eight Blocks of 8K × 16-Bit On-Chip
Dual-Access Program/Data RAM
Eight Blocks of 8K × 16-Bit On-Chip
Single-Access Program RAM
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144-Pin Ball Grid Array (BGA)(GGU Suffix)
144-Pin Low-Profile Quad Flatpack
(LQFP)(PGE Suffix)
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6.25-ns Single-Cycle Fixed-Point Instruction
Execution Time (160 MIPS)
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16K × 16-Bit On-Chip ROM Configured for
Program Memory
8.33-ns Single-Cycle Fixed-Point Instruction
Execution Time (120 MIPS)
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Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and Block-Repeat
Operations for Program Code
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3.3-V I/O Supply Voltage (160 and 120 MIPS)
1.6-V Core Supply Voltage (160 MIPS)
1.5-V Core Supply Voltage (120 MIPS)
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Block-Memory-Move Instructions for Better
Program and Data Management
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Instructions With a 32-Bit Long Word Operand
Instructions With Two- or Three-Operand
Reads
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and
Boundary Scan Architecture
TMS320C54x, TMS320 are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
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