TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
List of Figures
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144-Ball GGU MicroStar BGA™ (Bottom View) ............................................................................. 10
144-Pin PGE Low-Profile Quad Flatpack (Top View)....................................................................... 12
TMS320VC5416 Functional Block Diagram.................................................................................. 16
Program and Data Memory Map................................................................................................ 20
Extended Program Memory Map ............................................................................................... 21
Process Mode Status Register .................................................................................................. 22
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]......................... 23
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]......................... 24
Bank-Switching Control Register BSCR)[MMR Address 0029h] ........................................................... 25
Host-Port Interface — Nonmulltiplexed Mode................................................................................. 28
HPI Memory Map ................................................................................................................. 29
Multichannel Control Register (MCR1)......................................................................................... 31
Multichannel Control Register (MCR2)......................................................................................... 31
Pin Control Register (PCR) ...................................................................................................... 32
Nonconsecutive Memory Read and I/O Read Bus Sequence............................................................. 34
Consecutive Memory Read Bus Sequence (n = 3 reads).................................................................. 35
Memory Write and I/O Write Bus Sequence ................................................................................. 36
DMA Transfer Mode Control Register (DMMCRn) ........................................................................... 37
On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)......................................... 39
On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) .................................... 40
DMPREC Register ................................................................................................................ 41
General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]................................................ 44
General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] ................................................. 44
Device ID Register (CSIDR) [MMR Address 003Eh] ......................................................................... 44
IFR and IMR Registers ........................................................................................................... 50
Tester Pin Electronics ............................................................................................................ 54
Internal Divide-By-Two Clock Option With External Crystal ............................................................... 56
External Divide-By-Two Clock Timing......................................................................................... 58
Multiply-By-One Clock Timing.................................................................................................. 59
Nonconsecutive Mode Memory Reads ....................................................................................... 61
Consecutive Mode Memory Reads............................................................................................ 62
Memory Write (MSTRB = 0).................................................................................................... 63
Parallel I/O Port Read (IOSTRB = 0) ......................................................................................... 65
Parallel I/O Port Write (IOSTRB = 0).......................................................................................... 66
Memory Read With Externally Generated Wait States ..................................................................... 68
Memory Write With Externally Generated Wait States ..................................................................... 69
I/O Read With Externally Generated Wait States ........................................................................... 70
I/O Write With Externally Generated Wait States ........................................................................... 71
HOLD and HOLDA Timings (HM = 1)......................................................................................... 73
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List of Figures
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