TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
3.6 On-Chip Peripherals
The device has the following peripherals:
•
•
•
•
•
•
•
•
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8/16)
Three multichannel buffered serial ports (McBSPs)
A hardware timer
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
3.6.1 Software-Programmable Wait-State Generator
The software wait-state generator of the device can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY
line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state
generator are automatically disabled. Disabling the wait-state generator clocks reduces the power
consumption.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to
five separate address ranges. This allows a different number of wait states for each of the five address
ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control
register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the
wait-state generator is initialized to provide seven wait states on all external memory accesses. The
SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3.
15
14
12
11
9
8
XPA
I/O
R/W-111
5
DATA
R/W-111
2
DATA
R/W-0
7
6
3
0
DATA
PROGRAM
R/W-111
PROGRAM
R/W-111
R/W-111
LEGEND: R = Read, W = Write, n = value present after reset
Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address
0028h]
Functional Overview
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