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TMS320VC5416ZGU160 参数 Datasheet PDF下载

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型号: TMS320VC5416ZGU160
PDF下载: 下载PDF文件 查看货源
内容描述: TMS320VC5416定点数字信号处理器 [TMS320VC5416 Fixed-Point Digital Signal Processor]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 98 页 / 855 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320VC5416  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS095OMARCH 1999REVISED JANUARY 2005  
3.6.2 Programmable Bank-Switching  
Programmable bank-switching logic allows the device to switch between external memory banks without  
requiring external wait states for memories that need additional time to turn off. The bank-switching logic  
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program  
or data space.  
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped  
ataddress 0029h. The bit fields of the BSCR are shown in Figure 3-7 and are described in Table 3-5.  
15  
14  
13  
12  
11  
8
CONSEC  
DIVFCT  
R/W-11  
IACKOFF  
Reserved  
R
R/W-1  
7
R/W-1  
3
2
1
0
Reserved  
R
HBH  
BH  
Reserved  
R/W-0  
R/W-0  
R
LEGEND: R = Read, W = Write, n = value present after reset  
Figure 3-7. Bank-Switching Control Register BSCR)[MMR Address 0029h]  
Table 3-5. Bank-Switching Control Register (BSCR) Fields  
RESET  
VALUE  
BIT  
NAME  
FUNCTION  
Consecutive bank-switching. Specifies the bank-switching mode.  
CONSEC = 0: Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is  
desired for continuous memory reads (i.e., no starting and trailing cycles between read cycles).  
CONSEC  
15  
1
(1)  
CONSEC = 1: Consecutive bank switches on external memory reads. Each read cycle consists of  
3 cycles: starting cycle, read cycle, and trailing cycle.  
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency  
equal to 1/(DIVFCT+1) of the DSP clock.  
DIVFCT = 00: CLKOUT is not divided.  
14-13 DIVFCT  
11  
11  
DIVFCT = 01: CLKOUT is divided by 2 from the DSP clock.  
DIVFCT = 10: CLKOUT is divided by 3 from the DSP clock.  
DIVFCT = 11: CLKOUT is divided by 4 from the DSP clock (default value following reset).  
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.  
12  
IACKOFF  
Rsvd  
IACKOFF = 0: The IACK signal output off function is disabled.  
IACKOFF = 1: The IACK signal output off function is enabled.  
11-3  
Reserved  
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.  
HBH = 0: The bus holder is disabled except when HPI16 = 1.  
2
HBH  
0
0
HBH = 1: The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the  
previous logic level.  
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.  
BH = 0: The bus holder is disabled.  
1
0
BH  
BH = 1: The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous  
logic level.  
Rsvd  
Reserved  
(1) For additional information, see Section 3.11 of this document.  
Functional Overview  
25