TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
If the ROM-only security option is selected the following restrictions apply:
•
Only the on-chip ROM originating instructions can read the contents of the on-chip ROM; on-chip RAM
and external RAM originating instruction cannot read data from ROM: instead 0FFFFh is read. Code
can still branch to ROM from on-chip RAM or external program memory.
•
•
The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external
memory. To protect the internal RAM the user must never branch to external memory.
The security feature completely disables the scan-based emulation capability of the 54x to prevent the
use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG
boundary scan test capability.
•
•
The device can be started in either microcomputer mode or microprocessor mode at reset (depends on
the MP/MC pin).
HPI read and writes have no restriction.
3.5 Memory Map
The program and data memory map is shown in Figure 3-2. Address ranges for on-chip DARAM in data
memory are:
•
•
•
•
•
•
•
•
DARAM0: 0080h-1FFFh
DARAM1: 2000h-3FFFh
DARAM2: 4000h-5FFFh
DARAM3: 6000h-7FFFh
DARAM4: 8000h-9FFFh
DARAM5: A000h-BFFFh
DARAM6: C000h-DFFFh
DARAM7: E000h-FFFFh
Page 0 Program
Page 0 Program
Hex
Data
Hex
Hex
0000
0000
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
Memory-Mapped
Registers
(OVLY = 1)
External
005F
(OVLY = 0)
007F
0080
007F
0080
0060
007F
0080
Scratch-Pad
RAM
On-Chip
DARAM0−3
(OVLY = 1)
On-Chip
DARAM0−3
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0−3
(32K x 16-bit)
External
(OVLY = 0)
7FFF
8000
BFFF
C000
7FFF
8000
7FFF
8000
External
External
On-Chip
DARAM4−7
(DROM=1)
or
External
(DROM=0)
On-Chip ROM
(4K x 16-bit)
FF7F
FF80
FEFF
FF00
FF7F
FF80
FFFF
Interrupts
(External)
Reserved
Interrupts
(On-Chip)
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
Figure 3-2. Program and Data Memory Map
20
Functional Overview
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