TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
The device has an internal register that holds the MSB of the last address used for a read or write
operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of
the address used for the current read does not match that contained in this internal register, the MSTRB
(memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus
switches to the new address. The contents of the internal register are replaced with the MSB for the read
of the current address. If the MSB of the address used for the current read matches the bits in the
register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory
conflicts are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
•
•
•
•
A memory read followed by another memory read from a different memory bank.
A program-memory read followed by a data-memory read.
A data-memory read followed by a program-memory read.
A program-memory read followed by another program-memory read from a different page.
3.6.3 Bus Holders
The device has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers
of the address bus (A[17-0]), data bus (D[15-0]), and the HPI data bus (HD[7-0]). Bus keeper
enabling/disabling is described in Table 3-6.
Table 3-6. Bus Holder Control Bits
HPI16 PIN
BH
0
HBH
D[15-0]
OFF
OFF
ON
A[17-0]
OFF
OFF
OFF
OFF
OFF
ON
HD[7-0]
OFF
ON
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
OFF
ON
1
ON
0
OFF
OFF
ON
ON
0
ON
1
OFF
ON
ON
1
ON
ON
3.7 Parallel I/O Ports
The device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The device can
interface easily with external devices through the I/O ports while requiring minimal off-chip ad-
dress-decoding circuits.
26
Functional Overview
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