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TMS320VC5416ZGU160 参数 Datasheet PDF下载

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型号: TMS320VC5416ZGU160
PDF下载: 下载PDF文件 查看货源
内容描述: TMS320VC5416定点数字信号处理器 [TMS320VC5416 Fixed-Point Digital Signal Processor]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置时钟
文件页数/大小: 98 页 / 855 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320VC5416  
Fixed-Point Digital Signal Processor  
www.ti.com  
SPRS095OMARCH 1999REVISED JANUARY 2005  
Table 2-2. Signal Descriptions (continued)  
TERMINAL  
NAME  
I/O(1)  
DESCRIPTION  
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the  
emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is  
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into  
the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for  
multiprocessing applications). Therefore, for the OFF condition, the following apply:  
TRST = low,  
EMU1/OFF(6)  
I/O/Z  
EMU0 = high  
EMU1/OFF = low  
3
Functional Overview  
The following functional overview is based on the block diagram in Figure 3-1.  
P, C, D, E Buses and Control Signals  
64K RAM  
Dual Access  
Program/Data  
64K RAM  
Single Access  
Program  
16K Program  
ROM  
54X cLEAD  
MBus  
GPIO  
RHEA  
Bridge  
TI BUS  
RHEA Bus  
McBSP1  
XIO  
Enhanced XIO  
McBSP2  
McBSP3  
16HPI  
16 HPI  
xDMA  
logic  
RHEAbus  
TIMER  
APLL  
JTAG  
Clocks  
Figure 3-1. TMS320VC5416 Functional Block Diagram  
3.1 Memory  
The device provides both on-chip ROM and RAM memories to aid in system performance and integration.  
3.1.1 Data Memory  
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the  
on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds,  
the device automatically generates an external access.  
The advantages of operating from on-chip memory are as follows:  
Higher performance because no wait states are required  
Higher performance because of better flow within the pipeline of the central arithmetic logic unit  
(CALU)  
Lower cost than external memory  
16  
Functional Overview