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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
List of Figures
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
5-1
5-2
5-3
5-4
5-5
5-6
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5-9
5-10
5-11
5-12
5-13
5-14
144-Ball GGU MicroStar BGA™ (Bottom View)
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144-Pin PGE Low-Profile Quad Flatpack (Top View)
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TMS320VC5416 Functional Block Diagram
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Program and Data Memory Map
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Process Mode Status Register
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Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
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Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
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Bank-Switching Control Register BSCR)[MMR Address 0029h]
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Host-Port Interface — Nonmulltiplexed Mode
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HPI Memory Map
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Multichannel Control Register (MCR1)
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Multichannel Control Register (MCR2)
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Pin Control Register (PCR)
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Nonconsecutive Memory Read and I/O Read Bus Sequence
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Consecutive Memory Read Bus Sequence (n = 3 reads)
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Memory Write and I/O Write Bus Sequence
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DMA Transfer Mode Control Register (DMMCRn)
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On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
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On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
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DMPREC Register
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General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
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General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
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Device ID Register (CSIDR) [MMR Address 003Eh]
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IFR and IMR Registers
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Tester Pin Electronics
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Internal Divide-By-Two Clock Option With External Crystal
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External Divide-By-Two Clock Timing
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Multiply-By-One Clock Timing
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Nonconsecutive Mode Memory Reads
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Consecutive Mode Memory Reads
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Memory Write (MSTRB = 0)
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Parallel I/O Port Read (IOSTRB = 0)
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Parallel I/O Port Write (IOSTRB = 0)
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Memory Read With Externally Generated Wait States
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Memory Write With Externally Generated Wait States
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I/O Read With Externally Generated Wait States
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I/O Write With Externally Generated Wait States
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HOLD and HOLDA Timings (HM = 1)
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Extended Program Memory Map
List of Figures
5
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