TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
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Data Space (0000 - 005F)
Hex
0000
Reserved
001F
0020
DRR20
0021
DRR10
DXR20
0022
0023
DXR10
0024
Reserved
002F
DRR22
0030
DRR12
0031
DXR22
0032
0033
DXR12
0034
Reserved
0035
RCERA2
0036
0037
XCERA2
0038
Reserved
0039
003A
RECRA0
003B
XECRA0
003C
Reserved
003F
DRR21
0040
0041
DRR11
0042
DXR21
0043
DXR11
0044
Reserved
0049
004A
RCERA1
004B
XCERA1
004C
Reserved
005F
Data Space
0000
Data Space
(See Breakout)
005F
0060
007F
0080
1FFF
2000
3FFF
4000
Scratch-Pad
RAM
On-Chip
DARAM0
8K Words
On-Chip
DARAM1
8K Words
On-Chip
DARAM2
8K Words
On-Chip
DARAM3
8K Words
On-Chip
DARAM4
8K Words
On-Chip
DARAM5
8K Words
On-Chip
DARAM6
8K Words
On-Chip
DARAM7
8K Words
Hex
0000
I/O Space
5FFF
6000
Reserved
7FFF
8000
9FFF
A000
BFFF
C000
DFFF
E000
FFFF
FFFF
Figure 3-18. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4
DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5
DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management
schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed
separately and can be post-incremented, post-decremented, or post-incremented with a specified index
offset.
40
Functional Overview
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