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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095O – MARCH 1999 – REVISED JANUARY 2005
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver.
When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data
stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them.
Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of
particular channels for transmission and reception. All 128 channels in a bit stream consisting of a
maximum of 128 channels can be enabled.
15
Reserved
R
7
XPBBLK
6
XPABLK
5
4
XCBLK
R
2
10
9
XMCME
R/W
1
Reserved
R
8
XPBBLK
R/W
0
XMCM
R/W
R/W
R/W
LEGEND:
R = Read, W = Write,
n
= value present after reset
Figure 3-10. Multichannel Control Register (MCR1)
15
Reserved
R
7
RPBBLK
6
RPABLK
5
4
RCBLK
R
10
9
RMCME
R/W
8
RPBBLK
R/W
0
RMCM
R/W
2
1
Reserved
R
R/W
R/W
LEGEND:
R = Read, W = Write,
n
= value present after reset
Figure 3-11. Multichannel Control Register (MCR2)
The McBSP has two working modes:
•
In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the
normal 32-channel selection is enabled (default).
•
In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel
control register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME
= 1, twelve new registers ((R/X)CERC - (R/X)CERH) are used to enable the 128-channel selection.
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol.
Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported
by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is
configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or
as a slave.
Although the BCLKS pin is not available on the device PGE and GGU packages, the device is capable of
synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator
for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the
PCR to accommodate this option.
15
Reserved
R/W
7
SCLKME
6
CLKS STAT
14
13
XIOEN
R/W
5
DX STAT
12
RIOEN
R/W
4
DR STAT
11
FSXM
R/W
3
FSXP
10
FSRM
R/W
2
FSRP
9
CLKXM
R/W
1
CLKXP
8
CLKRM
R/W
0
CLKRP
31
Functional Overview
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