TMS320VC5416PGE160 参数 Datasheet PDF下载

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

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t

w(CIH)

t

c(CI)

X2/CLKIN

t

w(CIL)

t

r(CI)

t

f(CI)

t

c(CO)

t

d(CIH-CO)

CLKOUT

(see Note A)

t

f(CO)

t

r(CO)

t

w(COH)

t

w(COL)

A.

The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as

00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.

Figure 5-3. External Divide-By-Two Clock Timing

58

Electrical Specifications